1. Field of the Invention
The present invention relates to an analog-to-digital (AD) conversion method, an AD conversion apparatus, a solid-state imaging device, a solid-state imaging device driving method, and an imaging apparatus which can reduce the number of clock cycles necessary for performing AD conversion and also shorten a period of time necessary for AD conversion by preparing a digital-to-analog converter (DAC) reference signal for converting upper bits and by preparing that for converting lower bits.
2. Description of the Related Art
Solid-state imaging devices, such as a charge-coupled device (CCD) or a complementary metal oxide semiconductor (CMOS), have been used in many applications. Recently, a MOS-type solid-state imaging device which is suitable for
Next, basic operations of the MOS-type solid-state imaging device will be described.
In the MOS-type solid-state imaging device, the timing control circuit 119 selects unit pixels 111 in a row, and signal voltages of the unit pixels 111 selected are supplied to corresponding vertical signal lines.
Here, the DAC 115 and the comparator 116 and up/down counter 117 of a column are included in an AD converter circuit 120 employing a ramp DAC scheme. The AD converter circuit 120 converts an analog signal obtained from a pixel into a digital value.
The reference signal VREF generated by the DAC 115 is commonly supplied to comparators 116 of all columns, and the up/down counter 117 is independently provided to each of the columns.
The AD converter circuit 120 compares, at the comparator 116, a pixel signal that is output to the vertical signal line with the reference signal VREF whose value changes in steps, and obtains a digital value by incrementing or decrementing the up/down counter 117 during a period of time from a set time to the time when a magnitude relation between magnitude of a voltage of the pixel signal and that of the reference signal VREF is determined to be changed.
The pixel signal converted by the AD converter circuit 120 into the digital value is temporarily stored in the memory 118. Then, the value stored in the memory 118, which is a sequential memory, is read out by the column scanning circuit 114 to a horizontal output line, and thereby the read value is output outside the memory 118.
In many MOS-type solid-state imaging devices, when a pixel is reset, a voltage level of the vertical signal line is obtained, and then when light is incident on the pixel, a voltage level of the vertical signal line is obtained. Then, an operation for reducing a fixed-pattern noise due to an output circuit of each pixel is performed by obtaining a difference between the voltage level obtained when the pixel is reset and the voltage level obtained when light is incident on the pixel.
In the case of the MOS-type solid-state imaging device shown in FIG. 10, the up/down counter 117 is used to reduce the fixed pattern noise.
FIG. 11 is a timing chart showing operations of a MOS-type solid-state imaging device of the related art.
As shown in FIG. 11, first, a down-count operation is performed by using a counter when a reset level of a pixel is converted from analog to digital.
Next, an up-count operation starting from the count value for the reset level is performed by using the counter when light is incident on the pixel and when a voltage level of a vertical signal line of the pixel is converted from analog to digital when light is incident on the pixel. Thus, a difference in a digital domain can be obtained without using a subtracting circuit.
In the following description, a DAC-output ramp wave to which reference is made when AD conversion of the reset level is performed is referred to as a P-phase ramp wave, and a DAC-output ramp wave to which reference is made when AD conversion is performed when light is incident on the pixel is referred to as a D-phase ramp wave.
In such a MOS-type solid-state imaging device, with the refinement of fabrication techniques in recent years, it has become possible to provide a transistor of a smaller size in the comparator 116, and it is necessary to provide such a comparator to each of the columns. As a result, deviation in input voltages of the comparators 116 of the columns increases pixel noise.
In order to cope with this, an input offset voltage is maintained across the capacitors Cp25 and Cp26 of the comparator 116 as shown in FIG. 12, and thus the input offset voltage is corrected.
FIG. 12 is a schematic circuit diagram showing an example of the comparator 116 of the AD converter circuit 120 in a MOS-type solid-state imaging device of the related art.
In FIG. 12, a switch transistor Tr21 is connected between the gate and drain of a transistor Tr23, and a switch transistor Tr22 is connected between the gate and drain of a transistor Tr24.
A pixel signal propagating a vertical signal line is input to the gate of the transistor Tr24 via a capacitor Cp26, and the reference signal VREF supplied from the DAC 115 is input to the gate of the transistor Tr23 via a capacitor Cp25.
The comparator is a circuit which causes an output L27 to be at a “high” level or at a “low” level on the basis of a magnitude relation between a voltage level of the pixel signal and that of the signal from the DAC.
The input offset voltage can be corrected by maintaining deviation in a threshold voltage of a differential stage due to the use of a small transistor in the comparator and deviation in the gate length and gate width of transconductance of the transistor Tr23 across the capacitor Cp25 and maintaining the deviation in the threshold voltage of the differential stage due to the use of the small transistor in the comparator and deviation in the gate length and gate width of transconductance of the transistor Tr24 across the capacitor Cp26.
Moreover, since both correction of the offset voltage and redefining of an inverted voltage of the comparator can be performed, a direct-current component of the vertical signal line and that of the signal from the DAC can be negligible.
Therefore, not only a circuit can be designed without consideration of a direct-current component of the pixel signal output to the vertical signal line and that of the ramp wave from the DAC, but also changes in the inverted voltage of the comparator due to chip-to-chip variation generated during manufacturing thereof can be corrected.
Next, operations for correcting the input offset voltage in the example shown in FIG. 12 will be described. First, it is necessary to maintain an input offset voltage and also to determine a reference voltage used for comparison. Hereinafter, this determination operation is referred to as an auto-zero operation.
When the auto-zero operation is performed, a reset level of a pixel signal (a pixel reset level) is input from the vertical signal line, and an auto-zero base signal (an auto-zero base voltage) is input from the DAC.
A PSET signal for performing the auto-zero operation is commonly supplied to the gate of the switch transistor Tr21 and that of the switch transistor Tr22.
At the timing corresponding to the rising edge of the PSET signal, the switch transistors Tr21 and Tr22 are turned on, and the comparator reaches a state of equilibrium. That is, an operation point is determined where the gate voltage of the switch transistor Tr21 and that of the switch transistor Tr22 are identical, or, if the input offset voltage exists, the circuit reaches a state of equilibrium at a corrected offset voltage.
Next, at the timing corresponding to the falling edge of the PSET signal, the switch transistors Tr21 and Tr22 are turned off, and the gate of the transistor Tr23 and that of the transistor Tr24 become floating gates.
Here, a potential difference between the pixel reset level of the vertical signal line and the gate voltage of the transistor Tr24 is maintained across the capacitor Cp26, and a potential difference between the auto-zero reference voltage and the gate voltage of the transistor Tr23 is maintained across the capacitor Cp25.
By performing the auto-zero operation, magnitude of a signal of the vertical signal line and that of the ADC can be compared in a state in which an offset voltage of the comparator is corrected.
FIG. 13 is a timing chart showing an auto-zero signal, a pixel output of the vertical signal line, and a base signal supplied from the DAC in AD conversion which is performed on an image signal and which includes the auto-zero operation.
FIG. 14 is a timing chart showing that a voltage of the vertical signal line and a voltage of the reference signal supplied from the DAC reach a state of equilibrium of the comparator when the auto-zero reference voltage is maintained.
By performing the operation for determining the auto-zero reference voltage (eliminating a direct-current component of the voltage of a comparing target), as shown in FIG. 14, the pixel output of the vertical signal line and the DAC reference voltage reach the state of equilibrium of the comparator (an inverted voltage of the comparator) when the auto-zero reference voltage is maintained (at the timing corresponding to the falling edge of the PSET signal).
After this, AD conversion is performed two times in total by comparing the pixel reset level for the vertical signal line with the P-phase ramp wave for the DAC and by comparing an incoming light signal for the vertical signal line with the D-phase ramp wave for the DAC. As a result, digital conversion can be performed on the resulting image signal obtained by eliminating both an offset component due to the output circuit of each pixel and an offset component due to the auto-zero operation performed within each AD converter circuit from the image signal.